The present invention generally relates to a method for fabricating a split gate flash memory device and more particularly, relates to a method for fabricating square polysilicon spacers in a split gate flash memory device by a multi-step polysilicon etch process.
In the recent trend of development in semiconductor fabrication technology, the every increasing density of devices designed on a semiconductor wafer forces the design of components of smaller dimensions. The smaller the component size, the more number of components can be accommodated on a semiconductor wafer. In the recent advancement in fabrication technology, the dimensions of the components have been reduced to sub-micron sizes or smaller. In conjunction with the miniaturization of component sizes, multiple layers of interconnects have been used in forming components of multiple layers in a stack in order to reduce the horizontal real-estate the component occupies. For instance, one of such components that has miniaturized dimensions is a non-volatile memory device which includes programmable read-only memory (PROM), erasable programmable read-only memory (EPROM) and electrically erasable programmable read-only memory (EEPROM). The trend in the development of non-volatile memory devices is toward their long term durability and high operating speed.
A flash memory device is one of the non-volatile memory devices. It may include a floating gate for storing a charge and a charge input/output control unit. Flash memory devices have been widely used in portable computers and in the telecommunication industry. For instance, a flash memory device can be used as the basic input/output system for a personal computer. High-density non-volatile memory devices are used as large capacity memory for portable terminal devices and for interface cards between a digital camera and a personal computer.
One of the key elements in low voltage read/retrieve operations is the retrieval time. In order to meet the application requirement of a portable computing system, high efficiency and fast retrieval speed are important design considerations for a non-volatile memory device. Presently, a low voltage flash memory device operates under an operating voltage between 3 and 5 volts in order to charge or discharge the floating gate. Moreover, in a read-only memory device (ROM), electrons tunnel through an energy barrier between silicon and silicon oxide to enter into an oxidized conductive region. When a voltage is applied to the gate electrode, the electrical charge tunnels through the thin silicon nitride layer.
There are numerous methods for writing and erasing into a memory device, for instance, by controlling the base material, the electrical potential between the drain region, the source region and the gate electrode such that the tunneling electron can travel from the silicon through the thin oxidation layer. Inversely, the electron is emitted outwardly during an erasing operation. In order to gain reliability and quality of the components fabricated, the tunneling oxidation layer must have superior properties. Furthermore, the information stored in a flash memory device must depend on a longtime storage of the charge in the floating gate. As a result, the dielectric layer for insulating the floating gate must have superior properties.
Flash memory devices may be formed either in a stacked structure or in a split gate structure. As the name implies, a stacked structure flash memory device has the two gate electrodes stacked in an up-and-down manner, while the gate electrodes in a split gate structure is separated from each other. FIG. 1A shows an enlarged, cross-sectional view of a conventional method for forming a split gate memory device 10. Floating gates 12 and tunneling oxide layer 14 are formed on a silicon substrate 16. Silicon oxide structure 18 and the insulating spacers 20 are used for insulation. In-between the two floating gates 12, a The polysilicon via plug 22 is provided as the common source region. The polysilicon via plug is electrically connected to the source region 24 and insulated by an insulating layer 26 on top. A polysilicon layer 28, which is used as the word line, is then deposited on top of the structure 10.
In the next step of the process for the conventional split gate flash fabrication, the polysilicon layer 28 must be etched away. However, based on the etch characteristics, the polysilicon layer 28 is etched into a curved sidewall spacer 30, as shown in FIG. 1B, which causes processing difficulties for subsequent fabrication steps. For instance, when the large curvatured sidewall spacer 30 is used as a sidewall spacer for the formation of an LDD region, difficulty arises in the fabrication process which includes the bridging of metal silicides. It is therefore desirable that the large curvatured sidewall spacers can be formed into square shouldered spacers, in other words, the vertical side of the sidewall spacers should be formed 90xc2x0 with the horizontal surface.
It is therefore an object of the present invention to provide a method for forming polysilicon spacers on a split gate flash memory device that does not have the drawbacks or the shortcomings of the conventional method.
It is another object of the present invention to provide a method for forming polysilicon spacers on a split gate flash memory device that have square shoulders.
It is a further object of the present invention to provide a method for forming square polysilicon spacers on a split gate flash memory device by a multi-step polysilicon etch process.
It is another further object of the present invention to provide a method for forming square polysilicon spacers on a split gate flash memory device by depositing a sacrificial layer on top of the polysilicon sidewall spacer layer prior to the etching steps.
It is still another object of the present invention to provide a method for forming square polysilicon spacers on a split gate flash memory device by depositing a sacrificial layer on the polysilicon layer and then etching the spacers in two separate steps.
In accordance with the present invention, a method for forming square polysilicon spacers on a split gate flash memory device by multi-step polysilicon etch is provided.
In a preferred embodiment, a method for forming square polysilicon spacers on a split gate flash memory device by multi-step polysilicon etch can be carried out by the operating steps of first providing a pre-processed silicon substrate that has a split gate flash memory device formed thereon; depositing a polysilicon layer on top of the pre-processed silicon substrate; forming a sacrificial layer on top of the polysilicon layer; removing the sacrificial layer on top of the flash memory device, while leaving the sacrificial layer on the side of the flash memory device intact; etching away the polysilicon layer exposed on top of the split gate flash memory device; removing residual sacrificial layer on the side of the split gate flash memory device; and etching away the residual polysilicon layer anisotropically leaving square cornered polysilicon spacers on the split gate flash memory device.
The method for forming square polysilicon spacers on a split gate flash memory device may further include the step of forming the sacrificial layer with an insulating material, or the step of forming the sacrificial layer with silicon oxide, or the step of forming the sacrificial layer with silicon oxide by thermal oxidation. The method for forming square polysilicon spacers may further include the step of removing the sacrificial layer by a wet etch process, or the step of removing the sacrificial layer by an etchant including HF, or the step of removing the sacrificial layer by an etchant.
The present invention is further directed to a method for forming square polysilicon spacers on a split gate flash memory device by multi-step polysilicon etching including the steps of providing a semiconductor substrate; forming a tunneling oxide layer on top of the silicon substrate; depositing a polysilicon layer on top of the tunneling oxide layer; depositing a mask layer of insulating material on top of the polysilicon layer; removing the mask layer and defining the floating gate for the split gate flash memory device; forming insulating spacers on the sidewalls of the floating gate and the insulating material; forming a source region in the semiconductor substrate adjacent to the floating gate; forming a conductive via plug in-between the floating gate and the insulating material; forming an insulating layer on top of the conductive via plug; depositing a polysilicon layer on top of the conductive via plug, the floating gate and the insulating material structure; forming a sacrificial layer on top of the polysilicon layer; removing the sacrificial layer that overlies the floating gate, while maintaining the sacrificial layer on the sidewalls of the floating gate; etching away the polysilicon layer overlying the floating gate; etching away any residual sacrificial layer to expose the polysilicon layer underneath; and etching away any residual polysilicon layer to define the square-shaped polysilicon spacer on the split gate flash memory device.
The method for forming square polysilicon spacers on a split gate flash memory device by multi-step polysilicon etching may further include the step of forming the sacrificial layer with silicon oxide, or the step of forming the sacrificial layer with silicon oxide by thermal oxidation. The method may further include the step of removing the sacrificial layer with a wet etch technique, or the step of removing the sacrificial layer with an etchant including HF, or the step of removing the sacrificial layer with an etchant including BOE. The method may further include the step of forming the mask layer with Si3N4. The method may further include the step of forming the insulating structure by silicon oxide, or the step of forming the insulating structure with silicon oxide by thermal oxidation.